Physical & Design Verification
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Layout verse Schematic (LVS) Verification
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SkyWater
SkyWater SKY130 PDK
Table Of Contents
Versioning Information
Current Status
Known Issues
Design Rules
Background
Masks
Criteria & Assumptions
Layers Reference
Device and Layout vs. Schematic
Summary of Key Periphery Rules
Periphery Rules
WLCSP Rules
High Voltage Methodology
Very High Voltage Methodology
Antenna Rules
Parasitic Layout Extraction
Device Details
Error Messages
PDK Contents
Libraries
SkyWater Foundry Provided Standard Cell Libraries
sky130
_
fd
_
io
- SKY130 IO and periphery cells (SkyWater Provided)
User Guide for
sky130
_
fd
_
io
Critical Requirements Summary
File Types
Analog Design
With Cadence Virtuoso
With MAGIC
With Klayout
With Berkeley Analog Generator (BAG)
With FASoC
With your design flow?
Digital Design
With Cadence Innovus
With OpenROAD
With your design flow?
Simulation
With Cadence Spectre
With ngspice
With your design flow?
Physical & Design Verification
Automated Design Rule (DRC) Checking
With Mentor Calibre
With Magic
With KLayout
Layout Versus Schematic (LVS) Checking
With Mentor Calibre
With Magic
With KLayout
Parasitic Extraction (PEX)
With Mentor Calibre
With Magic
With KLayout
Python API
skywater_pdk package
Previous Nomenclature
Glossary
How to Contribute
Further Resources
Partners
SkyWater SKY130 PDK
Table Of Contents
Versioning Information
Current Status
Known Issues
Design Rules
Background
Masks
Criteria & Assumptions
Layers Reference
Device and Layout vs. Schematic
Summary of Key Periphery Rules
Periphery Rules
WLCSP Rules
High Voltage Methodology
Very High Voltage Methodology
Antenna Rules
Parasitic Layout Extraction
Device Details
Error Messages
PDK Contents
Libraries
SkyWater Foundry Provided Standard Cell Libraries
sky130
_
fd
_
io
- SKY130 IO and periphery cells (SkyWater Provided)
User Guide for
sky130
_
fd
_
io
Critical Requirements Summary
File Types
Analog Design
With Cadence Virtuoso
With MAGIC
With Klayout
With Berkeley Analog Generator (BAG)
With FASoC
With your design flow?
Digital Design
With Cadence Innovus
With OpenROAD
With your design flow?
Simulation
With Cadence Spectre
With ngspice
With your design flow?
Physical & Design Verification
Automated Design Rule (DRC) Checking
With Mentor Calibre
With Magic
With KLayout
Layout Versus Schematic (LVS) Checking
With Mentor Calibre
With Magic
With KLayout
Parasitic Extraction (PEX)
With Mentor Calibre
With Magic
With KLayout
Python API
skywater_pdk package
Previous Nomenclature
Glossary
How to Contribute
Further Resources
Partners
Warning
This page was created from a pull request.
Layout verse Schematic (LVS) Verification
ΒΆ
With Mentor Calibre
With Magic
With KLayout
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